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AS5045
Data Sheet
6.7.2
Pulse Width Modulation Output
(operating conditions: T amb = -40 to +125°C, VDD5V = 3.0~3.6V (3V operation) VDD5V = 4.5~5.5V (5V operation)
unless otherwise noted)
Parameter
PWM frequency
Minimum pulse width
Maximum pulse width
Symbol
f PWM
PW MIN
PW MAX
Min
232
220
0.95
3891
Typ
244
244
1
4096
Max
256
268
1.05
4301
Unit
Hz
μs
μs
Note
Signal period = 4097μs ± 5% at T amb = 25°C
= 4097μs ± 10% at T amb = -40 to +125°C
Position 0d; Angle 0°
Position 4095d; Angle 359.91°
Note: when OTP bit “PWMhalfEn” is set, the PWM pulse width PW is doubled (PWM frequency f PWM is divided by 2)
6.8 Programming Conditions
(operating conditions: T amb = -40 to +125°C, VDD5V = 3.0~3.6V (3V operation) VDD5V = 4.5~5.5V (5V operation)
unless otherwise noted)
Parameter
Programming enable time
Symbol
t Prog enable
Min
2
Typ
Max
Unit
μs
Note
Time between rising edge at
Prog pin and rising edge of CSn
Write data start
t Data in
2
μs
Write data valid
Load programming data
Rise time of V PROG before
CLK PROG
t Data in valid
t Load PROG
t PrgR
250
3
0
ns
μs
μs
Write data at the rising edge of
CLK PROG
Hold time of V PROG after
CLK PROG
t PrgH
0
5
μs
Write data – programming
CLK PROG
CLK PROG
250
kHz
Ensure that V PROG is stable with
rising edge of CLK
CLK pulse width
Hold time of Vprog after
programming
Programming voltage, pin
PROG
Programming voltage off level
Programming current
Analog read CLK
Programmed Zener voltage
(log.1)
Unprogrammed Zener voltage
(log. 0)
t PROG
t PROG finished
V PROG
V ProgOff
I PROG
CLK Aread
V programmed
V unprogrammed
1.8
2
7.3
0
1
2
7.4
2.2
7.5
1
130
100
100
μs
μs
V
V
mA
kHz
mV
V
During programming; 16 clock
cycles
Programmed data is available
after next power-on
Must be switched off after
zapping
Line must be discharged to this
level
During programming
Analog Readback mode
V Ref -V PROG during Analog
Readback mode (see 11.4)
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Revision 1.7
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